The present invention relates generally to the field of processor microarchitecture and more particularly to the scheduling and issuing of instructions to execution units in a processor.
A processor often fetches instructions from an instruction cache into an issue unit (an issue queue), from which the instructions are issued to one or more execution units for execution. Instructions are issued from an issue queue, when appropriate conditions are met, to execution units or to reservation stations associated with the execution units. It is often advantageous to issue an instruction that has been in the issue queue the longest (i.e., the oldest instruction in the queue), out of all instructions in the queue that are ready to execute. It is more likely that other instructions are waiting for the data produced by the oldest instruction than for data produced by a younger instruction in the issue queue.
The logic in the issue queue is often a critical path of the logic in the processor, i.e., the cycle time of the processor (and therefore often its performance) may depend on the speed of the issue queue. Several factors influence the speed of an issue queue, e.g., the number and type of logic gates in its critical path and the physical distances between the gates, which is influenced by the area consumed by its logic and signal paths. The area consumed by signal paths tends to spread logic out, increasing the distance between logic gates, and causing signal paths to lengthen. The increase in the length of signal paths increases the capacitance of the paths (potentially increasing energy consumption) and increases the propagation delay between the logic gates, which can increase cycle time and decrease performance. Issue queue structures that are capable, area efficient, and fast are an active area of research and development.